Supercomputing startup Ceremorphic has unveiled plans to deliver a complete silicon system built on 5 nanometer infrastructure.
The company says its system will provide the performance needed for next-generation applications such as artificial intelligence model training, high-performance computing, automotive processing, drug discovery, and metaverse processing.
Designed in advanced silicon geometry (TSMC 5nm node), this new architecture was built from the ground up to solve today’s high-performance computing problems in reliability, security and energy consumption to serve all performance-demanding market segments.
Ceremorphic was founded in April 2020 by industry-veteran Dr Venkat Mattela, the Founding CEO of Redpine Signals, which sold its wireless assets to Silicon Labs in March 2020 for $308 million.
Under his leadership, the team at Redpine Signals delivered breakthrough innovations and industry-first products that led to the development of an ultra-low-power wireless solution that outperformed products from industry giants in the wireless space by as much as 26 times on energy consumption.
Ceremorphic leverages its own patented multi-thread processor technology ThreadArch combined with cutting-edge new technology developed by the silicon, algorithm and software engineers currently employed by Ceremorphic.
This team is leveraging its deep expertise and patented technology to design an ultra-low-power training supercomputing chip.
Venkat Mattela, founder and CEO of Ceremorphic, says: “Having developed many innovations in multi-thread processing, algorithm driven VLSI, reliable performance circuits, low-energy interface circuits, quantum resistant security microarchitecture, and new device architectures beyond CMOS, Ceremorphic is well on its way to accomplish our goals.
“The challenges this market faces with ‘reliable performance computing’ cannot be solved with existing architectures, but rather needs a completely new architecture built specifically to provide reliability, security, energy efficiency, and scalability.”
Mattela adds: “We strongly believe that building a technology foundation is key to developing highly differentiated products that can lead the industry.
“We proved that in the wireless space with Redpine Signals and we are now doing the same thing in the computing space with Ceremorphic.”
Subhasish Mitra, professor of electrical engineering and of computer science at Stanford University, says: “I am very impressed with the Ceremorphic approach to solving some of the key challenges in the reliability and performance computing space today.
“Reliable performance computing is absolutely something this industry needs and the approach that Ceremorphic is pursuing is a significant step in the right direction.”
Hierarchical Learning Processor (HLP) deploys the right processing system for optimal power performance operation. Key features of the QS 1 include the following:
- Custom Machine Learning Processor (MLP) running at 2GHz
- Custom FPU running at 2GHz
- Patented Multi-thread processing macro-architecture, ThreadArch® based RISC –V® processor for proxy processing (1GHz)
- Custom video engines for Metaverse Processing (1GHz) along with M55 v1 core from ARM®
- Custom designed X16 PCIe 6. 0 / CXL 3.0 connectivity interface
- Open AI framework software support with optimized compiler and application libraries
- Soft error rate: (100,000)-1
The Ceremorphic architecture has been designed to scale across multiple compute intensive markets and applications, including AI training supercomputing, data center processing, automotive, metaverse processing, robotics and life sciences.